In general, a nonvolatile memory such as a flash memory does not lose data stored therein even if power is turned off Therefore, the flash memory has been extensively used for a Bios of a personal computer (PC), a set-top box, a printer, and a network server in order to store data. Recently, the flash memory is prevalent in digital cameras, and portable phones.
The flash memory is an EEPROM capable of performing erasing and programming operations in a block unit other than a byte unit. The typical flash memory includes a memory array having a plurality of memory cells. Each memory cell includes a floating gate field effect transistor (FET) capable of retaining charges. Data in the cell are determined depending on the charges in the floating gate. The cell is divided into sections typically called “erase blocks”. The memory cells of the flash memory array are typically arranged in the form of “NOR” architecture (each cell is directly connected to a bit line) or “NAND” architecture (cells are prepared as “strings” of cells so that each cell is indirectly connected to a bit line and other cells of a string must be activated for the purpose of access). Each cell of the erase block can be electrically programmable in a random basis by charging the floating gate. The charge can be erased from the floating gate through the block erase operation and all floating gate memory cells in an erase block can be erased at one time.
Recently, an NROM (nitride read only memory) is extensively used as a flash memory. The NROM has some characteristics of the flash memory without requiring complicated manufacturing processes for the flash memory. NROM integrated circuits can be realized through a standard CMOS process. Due to the intrinsic device characteristics of the memory, some NROM memory cells can store a plurality of data bits (for instance, 2 bits in each cell).
FIG. 1 is a cross-sectional view showing a planar type NROM flash memory device.
Referring to FIG. 1, an NROM device includes a semiconductor substrate 10 formed with source and drain regions 11 and 13. An ONO pattern 16 including an oxide layer 16c, a nitride layer 16b and an oxide layer 16a are formed between the source and drain regions 11 and 13, and a control gate 15 is formed on the ONO pattern 16. The nitride layer 16b of the ONO pattern 16 may serve as a trapping layer 19 for trapping charges from a channel.
The NROM memory cell has a structure similar to a structure of a MOSFET transistor, so the gate 15 is isolated from the channel, the source, and the drain by the ONO pattern 16. An isolated trapping layer is buried in the ONO pattern 16. Current may flow when the NROM memory cell/transistor is selected or activated. The charges trapped in the trapping layer exert an influence upon the quantity of current depending on the operational direction (current flow in the channel) of the NROM transistor, thereby effectively increasing or decreasing the threshold value of current in the operational direction of the NROM transistor.
According to the operation of the conventional NROM device, when the NROM device is programmed through an HCI (hot carrier injection) scheme and erased through a BTBT (band to band tunneling) hot hole scheme, holes and electrons are stacked in areas different from each other due to difference in distribution between electrons and holes.
Due to the above difference in distribution, the trapped charges may be subject to lateral diffusion so that the retention threshold voltage (Vt) characteristics may be degraded. As several periods repeat, the program Vt is gradually increased and the erase Vt is gradually reduced, so that the Vt window becomes gradually narrowed.
That is, in the typical NROM flash memory device, the position of the charges may not be changed after the charges have been trapped in the trap layer, so the device characteristics may be changed and reliability may deteriorate even if the trap positions of the electrons and the holes are slightly changed.